Microelectronics Papers and Presentations:
(36) H.S. Yang, et.al., "Scaling of 32nm Low Power SRAM with High-K Metal Gate", IEEE IEDM Proceedings, Dec., 2008.
(35) X. Chen, et.al., "A Cost Effective 32nm High-K/ Metal Gate CMOS Technology for Low Power Applications with Single-Metal/Gate-First Process", Proceedings of the Symposium on VLSI Technology, 2008.
(34) G C-F. Yeap, et. al., "A 100nm CopperLow-K Bulk CMOS Technology with Multi Vt and Multi Gate Oxide Integrated Transistors for Low Standby Power, High Performance and RF/Analog System on Chip Applications", Proceedings of the Symposium on VLSI Technology, 2002.
(33) S. Parihar, et. al., "A High Density 0.10um CMOS Technology Using Low K Dielectric and Copper Interconnect", IEEE IEDM Proceedings, Dec., 2001.
(32) G. C-F. Yeap, et.al., "A 180nm Copper/Low-K CMOS Technology with Dual Gate Oxide Optimized for Low Power and Low Cost Consumer Wireless Applications", Proceedings of the Symposium on VLSI Technology, 2000.
(31) M. Bhat, et.al., "A Highly Versatile 0.18um CMOS Technology with Dense Embedded SRAM", Proceedings of the Symposium on VLSI Technology, 2000.
(30) S. Poon, C. Atwell, C. Hart, D. Kolar, C. Lage, B. Yeargain, "A versatile 0.25 micron CMOS technology", IEEE IEDM Proceedings, Dec., 1998.
(29) M. Woo, et.al., "A High-Performance 3.97um2 CMOS SRAM Technology using Self-Aligned Local Interconnect and Copper Metallization", Proceedings of the Symposium on VLSI Technology, 1998.
(28) C. Lage, J.D. Hayden, C. Subramanian, "Advanced SRAM Technology – The Race Between 4T and 6T Cells", IEEE IEDM Proceedings, Dec., 1996.
(27)S. Venkatesan, J.W. Lutze, C. Lage, W.J. Taylor, "Device Drive Current Degradation Observed with Retrograde Channel Profiles", IEEE IEDM Proceedings, Dec., 1995.
(26)R.C.Taft, C.S.Lage, J.D.Hayden, H.C.Kirsch, J.-H.Lin, D.J. Denning, F.B. Shapiro, D.E. Bockelman, N. Camilleri, "The SCC BJT: A High-Performance Bipolar Transistor Compatible with High-Density Deep-Submicrometer BiCMOS SRAM Technologies", IEEE Transactions on Electron Devices, July, 1995.
(25)A.H. Perera, C.S. Lage, J.D. Hayden, J.-H. Lin, R. Rodriguez, S. Ajuria, "Short-Channel Vertical NMOSFET's for High Density Fast SRAM's", IEEE IEDM Proceedings, Dec., 1994.
(24)J.D.Hayden, R.C.Taft, P. Kenkare, C. Mazuré, C. Gunderson, B.-Y. Nguyen, M. Woo, C. Lage, B.J. Roman, S. Radhakrishna, R. Subrahmanyan, A.R. Sitaram, P. Pelley, J.-H. Lin, K. Kemp, H. Kirsch, "A Quadruple Well, Quadruple Polysilicon BiCMOS Process for Fast 16Mb SRAM's", IEEE Transactions on Electron Devices, Dec., 1994.
(23)C. Lage, D.Burnett, T.McNelly, K.Baker, A.Bormann, D.Dreier, V.Soorholtz, "Soft Error Rate and Stored Charge Requirements in Advanced High-Density SRAMs", IEEE IEDM Proceedings, Dec., 1993.
(22) S.Poon, C. Lage, "A Trench Isolation Process for BiCMOS circuits", IEEE BCTM Proceedings, Oct., 1993.
(21) J.D.Hayden, J.D.Burnett, A.H.Perera, T.C.Mele, F.W.Walczyk, V.Kaushik, C.S.Lage, Y-C.See, "Integration of a Double-Polysilicon Emitter-Base Self-Aligned Bipolar Transistor into a 0.5µm BiCMOS Technology for Fast 4-Mb SRAM's", IEEE Transactions on Electron Devices, Vol.40, No.6, Jun., 1993.
(20)D. Burnett, C. Lage, A. Bormann, "Soft-Error-Rate Improvement in Advanced BiCMOS SRAM's", IEEE IRPS Proceedings, Apr., 1993.
(19)A.H. Perera, C. Lage, A.R. Sitaram, M.P. Woo, S. Tatti, "Thermally Robust TiSi2 on Heavily Doped Polycrystalline Silicon over Severe Topography", IEEE IEDM Proceedings, Dec., 1992.
(18)C. Lage, "BiCMOS Process Technology for High-Speed Four Megabit SRAMs", GOMAC Digest of Technical Papers, Nov., 1992.
(17)F. Walczyk, C. Lage, V. Kaushik, M. Blackwell, "Tailoring Interfacial Oxide for Polysilicon Bit-Cell Contacts and Emitters with in-situ Vapor HF Interface Cleaning and Polysilicon Deposition in a 4 MBit BiMOS Fast Static RAM", IEEE BCTM Proceedings, Oct., 1992.
(16)Yeong-Seuk Kim, David Burnett, and Craig S. Lage, "New Method for Determining the Reverse Transit Time in Bipolar Transistors", IEEE Transactions on Electron Devices, Oct., 1992.
(15)Craig Lage, "BiCMOS Memories: Increasing Speed While Minimizing Process Complexity", Solid State Technology, Aug., 1992.
(14)J.D. Hayden, T.C. Mele, A.H. Perera, J.D. Burnett, F.W. Walczyk, C.S. Lage, F.K. Baker, M. Woo, W. Paulson, M. Lien, Y.C. See, D. Denning, S.J. Cosentino, "A High-Performance 0.5 µm BiCMOS Technology for Fast 4-Mb SRAM's", IEEE Transactions on Electron Devices, July, 1992.
(13)J.D. Burnett, C. Lage, J. D. Hayden, "Bipolar Reliability Optimization Through Surface Compensation of the Base Profile", IEEE IRPS Proceedings, Apr., 1992.
(12)J.D. Hayden, J.D. Burnett, A.H. Perera, T.C. Mele, F.W. Walczyk, V. Kaushik, C.S. Lage, Y.C. See, "Integration of a Double Polysilicon, Fully Self-Aligned Bipolar Transistor into a 0.5 µm BiCMOS Technology for Fast 4 MBit SRAMs", IEEE BCTM Proceedings, Oct., 1991.
(11) W.R. Burger, C. Lage, B. Landau, M. DeLong, J. Small, "An Advanced 0.8 µm Complementary BiCMOS Technology for Ultra-High Speed Circuit Performance", IEEE BCTM Proceedings, Oct., 1990.
(10) W.R. Burger, C. Lage, T. Davies, M. Delong, D. Haueisen, J. Small, G. Huglin, B. Landau, F. Whitwer, B. Bastani, "An Advanced Self-Aligned BiCMOS Technology for High Performance 1 Megabit ECL I/O SRAM's", IEEE IEDM Proceedings, Dec., 1989.
(9) F. Whitwer, D. Milligan, J. Garner, S-P. Sun, M. Shenasa, T. Davies, C. Lage, "A Submicron, Double-Level-Metal Process for High Density Memory Applications", Proceedins of the VLSI Multilevel Interconnect Conference, pp 49-54, 1990.
(8) B. Bastani, M. Biswal, A. Iranmanesh, C. Lage, L. Bouknight, V. Ilderem, A. Solheim, W. Burger, R. Lahri, J. Small, "Submicron BiCMOS Technologies for Super Computer and High Speed System Implementation", Proceedings of the Symposium on VLSI Technology, pp 7-10, 1990.
(7) F. Whitwer, T. Davies, C. Lage, "Premetal Planarization Using Spin-on Dielectric", Proceedings of the VLSI Multilevel Interconnect Conference, 1989.
(6) F. Whitwer, F. Haas, C. Lage, "The Influence of Titanium Capped Aluminum on N+/P+ Junction Leakage", Proceedings of the VLSI Multilevel Interconnect Conference, 1987.
(5) S.P. Joshi, R. Lahri, C. Lage, "Poly Emitter Bipolar Hot Carrier Effects in an Advanced BiCMOS Technology", IEEE IEDM Proceedings, pp 182-185, Dec., 1987.
(4) B. Bastani, C. Lage, L. Wong, J. Small, R. Lahri, L. Bouknight, T. Bowman, J. Maniliou, P. Tuntasood, "Advanced One Micron BiCMOS Technology for High Speed 256K SRAMS", Proceedings of the Symposium on VLSI Technology, pp 41-42, 1987.
(3) K.Y. Chiu, J.L. Moll, K.M. Cham, J. Lin, C. Lage, S. Angelos, R.L. Tillman, "The Sloped-Wall Swami - A Defect-Free Zero Bird's-Beak Local Oxidation Process for Scaled VLSI Technology", IEEE Transactions on Electron Devices , pp 1506-1511, 1983.
(2)D.E. Hackleman, N.L. Johnson, C.S. Lage, J.J. Vietor, R.L. Tillman, "CMOSC: Low-Power Technology for Personal Computers", Hewlett-Packard Journal, Jan., 1983.
(1)K.Y. Chiu, R. Fang, J. Lin, J.L. Moll, C. Lage, S. Angelos, R. Tillman, "The SWAMI - A Defect Free and Near-Zero Bird's-Beak Local Oxidation Process and its Application in VLSI Technology", IEEE IEDM Proceedings, Dec., 1982.